搜索资源列表
8051IPcore，verilogHDL实现
- 用verilog写的很好的cpu core-using Verilog write a good cpu core
ARMCORE
- 用verilog语言实现的ARM7处理器的标准内核的源代码程序,nnARM, 具有很好的参考价值-using Verilog language of the standard ARM7 processor core source code procedures nnARM, who have a good reference value
aes_core
- AES高级加密算法的verilog语言实现。同时附有AES协议的pdf文档，和此代码的测试程序，可作为一个IP核直接使用，可减少开发人员的设计时间。-AES Advanced Encryption Algorithm Verilog language. While the agreement with AES pdf documents, and that this code of the test procedure can be used as an IP core direct use,
ARM_Core
- arm verilog hdl ip core-arm Verilog HDL core ip
AUDIO_DAC
- 一个关于声音处理的Verilog语言编写的解码芯片，可以用于FPGA处理芯片的IP核，欢迎大家来用。-a voice on the Verilog language decoder chip, FPGA can be used to handle IP core chips, all are welcome to use.
sarm9beta
- arm9 架构简单core实现，可以综合，有实现步骤和说明，verilog代码编写。-arm9 core framework to achieve a simple, comprehensive, implementation steps and notes verilog code prepared.
my_ip_core
- 在quartusII下用verilog语言自己写的IP核，对FPGA开发初学者有帮助的。-in quartusII verilog using their own language to write the IP core, FPGA development beginners to help.
DCTofJPEG
- 用verilog代码写的JPEG压缩核心模块DCT变换之蝶形单元算法-verilog code written using JPEG compression core module DCT's butterfly modules algorithm
vspi
- verilog VSIP core,用verilog语言编写，希望对各位朋友有所帮助！
Module基础全集
- 如题，各种veirlog 基础代码大全，虽功能不及ip核，但却可以学习到很多(For example, all kinds of veirlog base code, though not as functional as IP core, can learn a lot)
SHA256_SYSTEM
- 利用硬件（可编程逻辑器件FPGA）实现密码算法SHA256，在FPGA中嵌入软核NIOSii，在NIOSii上进行软件编程。 硬件EDA工具为ALTERA的Quartus ii，软件IDE为eclipse（嵌在Quartua中）。(The hardware (programmable logic device FPGA) is used to implement the cryptographic algorithm SHA256, and the soft core NIOSii is em
高大上欧美风商务PPT模板
- JPEG_d IP Core Verilog crypted source
iir_2n_ip_float_demo
- 使用altera提供的ip核，实现了浮点数运算的2阶iir滤波器，结果与matlab运算结果相同。(Using the IP core provided by Altera, the 2 order IIR filter of floating point operation is implemented, and the result is the same as that of MATLAB operation.)
at7_ex04
- 通过LED闪烁控制器的代码，使用Vivado工具配置定义一个IP核，在用户工程中可随意添加这个IP核作为设计的一部分，如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at rando
Audio_whistle_suppressor
- 探讨了一种数字移频法啸叫检测与抑制音频功率放大实验测试系统设计方案，用来实现带啸叫检测与抑制音频功率放大．系统以 FPGA 为控制核心(This paper has designed a testing system for an audio power amplifier with howling detection and suppression which is used to achieve howling detection and suppression audio power am
FIR设计实现sgh
- FIR滤波FPGA实现 ，已在仿真软件上验证实现，不是IP核，不是ip核。(FIR filter FPGA implementation, has been verified in the simulation software, not IP core, not IP core.)
8051Core
- 8051 Core Verilog RTL IP Code
PLL
- 本次的设计主要任务是学会调用锁相环 IP 核，并对其进行仿真， 具体要求如下：（1）熟练掌握调用锁相环 IP 核的详细步骤。将 50M 的时钟分成 20MHz 和 100MHz 两个时钟（2）对锁相环进行仿真，验证 调用的锁相环的正确性。(The main task of this design is to learn to call the phase-locked loop IP core.)
Actel8051Core
- Actel 8051 Verilog core
cordic
- 该程序实现了Cordic算法，未调用IP核通过Cordic算法进行三角函数运算(This program implements Cordic algorithm and does trigonometric function operation through Cordic algorithm without calling IP core.)